-------------------------------------------------------------
--    _____
--   /     \	
--  /____   \____
-- / \===\   \==/
--/___\===\___\/  AVNET
--     \======/   DESIGN
--      \====/    SERVICES
--
--------------------------------------------------------------
--
-- Title       : ac97_top.vhd
-- Design      : 
-- Author      : James Dampare 
-- Company     : Avnet
-- Date        : 01/09/2003
---------------------------------------------------------------

LIBRARY ieee ;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
use IEEE.std_logic_unsigned.all;

entity ac97_top is
  port(
      sysclk                : in  std_logic;   -- 25.175 MHz
      reset_on              : in  std_logic; 
      reset_off             : in  std_logic;                                                 
      bit_clk               : in  std_logic;   -- 12.288 MHz
      LED                   : out std_logic_vector(7 downto 0);

      -- UCB1400 Codec Interface
      sdata_in              : in  std_logic; 
      sdata_out             : out std_logic;
      sync_out              : out std_logic;
      ac97_reset_n          : out std_logic;
      test_data             : out std_logic_vector(15 downto 0)
 );          
end ac97_top;  


architecture rtl of ac97_top is

-----------------------------
--  Declare Components
-----------------------------
component ac97_cntl  
port(
    sysclk                : in  std_logic;   
    reset_on              : in  std_logic;
    reset_off             : in  std_logic;                                                    
    bit_clk               : in  std_logic; 
    LED                   : out std_logic_vector(6 downto 0);
    sdata_in              : in  std_logic; 
    sdata_out             : out std_logic;
    sync_out              : out std_logic;
    ac97_reset_n          : out std_logic;
    test_data             : out std_logic_vector(15 downto 0)
   );
end component;

-------------------------------------------------------------------------------
signal LED_int           : std_logic_vector(6 downto 0);


--------------------------------------------------------------------------------
	
begin 

LED(0) <= LED_int(0);
LED(1) <= LED_int(1);
LED(2) <= LED_int(2);
LED(3) <= LED_int(3);
LED(4) <= LED_int(4);
LED(5) <= LED_int(5);
LED(6) <= LED_int(6);
LED(7) <= reset_on;

--------------------------------
--  COMPONENT Instantiations
--------------------------------

inst_ac97_cntl: ac97_cntl 
port map(
   sysclk        => sysclk,
   reset_on      => reset_on,
   reset_off     => reset_off,			 
   bit_clk       => bit_clk,
   LED           => LED_int,
   sdata_in      => sdata_in,	
   sdata_out     => sdata_out,
   sync_out      => sync_out,
   ac97_reset_n  => ac97_reset_n,
   test_data     => test_data
   );
------------------------------------------------- 

end rtl; 
